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Those are the I/O chips (plus a few other functions) found in Master System consoles.

I reversed them and even tested repros in CPLDs some years ago, following a repair I had made on a MS2 with a partially faulty 315-5237 (some inputs were stuck low = buttons seen as pressed).

After reading a message from @willbritton on Discord I decided to document my work better (I'm terrible at documenting things...).

Following two posts, one for each chip.

315-5216

First, there are some mistakes there:
https://www.smspower.org/Development/IOCtrlPinouts
- pin 22 is connected to the reset button on MS1
- !KILLGA (pin 23) & !CSRAM (pin 24) are both inputs

The equations:

I always start my designs using either an ATF1508 or an EPM7128 in PLCC84 for their high number of I/Os and macrocells, then once I reach a working design I try to find the smallest device it could fit in (both in terms of I/Os and macrocells). In that case an ATF1504/EPM7064 is enough, 40 I/Os are needed which discards the 44 pin devices, 68 pin ones are pretty much unobtainable, the nice and small TQFP100s are expensive, so I sticked to the "big" PLCC84 version. I'll try to post a picture of the repro PCB, it's not the best aesthetically... Feel free to adapt the code below to your targeted chip of choice.

[EDIT]
I've declared two more nodes to reduce drastically macrocell count. Now requires only 32.

Name 315-5216;
PartNo 00;
Date 12/06/2019;
Revision 01;
Designer Apocalypse;
Company PC;
Assembly None;
Location ;
Device f1504ispplcc84;

PROPERTY ATMEL {TDI_pullup = ON};
PROPERTY ATMEL {TMS_pullup = ON};
PROPERTY ATMEL {power_reset= ON};

/****************************************************************/
/* */
/* General File Comments */
/* */
/****************************************************************/

/*
* Pins: define pins in this section
*/

Pin 4 = CE0; /* 1 - O */
Pin 5 = CE1; /* 2 - O */
Pin 6 = CE2; /* 3 - O */
Pin 8 = CE3; /* 4 - O */
Pin 9 = CE4; /* 5 - O */
Pin 10 = D0; /* 6 - IO */
Pin 11 = D1; /* 7 - IO */
Pin 12 = D2; /* 8 - IO */
/* Pin 14 = TDI */
Pin 15 = D3; /* 9 - IO */
Pin 16 = D4; /* 10 - IO */
Pin 17 = D5; /* 12 - IO */
Pin 18 = D6; /* 13 - IO */
Pin 21 = D7; /* 14 - IO */
Pin 22 = A0; /* 15 - I */
/* Pin 23 = TMS */
Pin 24 = A6; /* 16 - I */
Pin 25 = A7; /* 17 - I */
Pin 27 = MREQ; /* 18 - I */
Pin 28 = IOREQ; /* 19 - I */
Pin 29 = RD; /* 20 - I */
Pin 30 = WR; /* 21 - I */
Pin 31 = CONT1; /* 22 - I */
Pin 33 = KILLGA; /* 23 - I */
Pin 34 = CSRAM; /* 24 - I */
Pin 35 = UP1; /* 25 - I */
Pin 36 = DN1; /* 26 - I */
Pin 37 = LE1; /* 27 - I */
Pin 39 = RI1; /* 28 - I */
Pin 40 = TL1; /* 29 - I */
Pin 41 = TR1; /* 30 - IO */
Pin 44 = TH1; /* 31 - IO */
Pin 45 = HL; /* 33 - O */
Pin 48 = TH2; /* 34 - IO */
Pin 49 = TR2; /* 35 - IO */
Pin 50 = TL2; /* 36 - I */
Pin 51 = RI2; /* 37 - I */
Pin 52 = LE2; /* 38 - I */
Pin 54 = DN2; /* 39 - I */
Pin 55 = UP2; /* 40 - I */
Pin 56 = RST; /* 41 - I */
Pin 57 = CONT2; /* 42 - I */
/* Pin 62 = TCK */
/* Pin 71 = TDO */

/*
* Nodes: define nodes as active HI levels in this section
*/

Node [PORT_3E_B7..0];
Node [PORT_3F_B7..0];

Node WR_3E;
Node WR_3F;

/*
* Fields: define fields in this section
*/

Field PORT_3E = [PORT_3E_B7..0];
Field PORT_3F = [PORT_3F_B7..0];
Field PORT_DC = [DN2,UP2,TR1,TL1,RI1,LE1,DN1,UP1];
Field PORT_DD = [TH2,TH1,CONT2,CONT1,TR2,TL2,RI2,LE2];
Field DATA = [D7..0];

/*
* Logic: logic equations in this section
*/

/* PORT $3E */
/* Init = 0xE0 */

WR_3E = !A7 & !A6 & !A0 & !WR & !IOREQ & !KILLGA;

PORT_3E_B7 = PORT_3E_B7 & !WR_3E # D7 & WR_3E # !RST;
PORT_3E_B6 = PORT_3E_B6 & !WR_3E # D6 & WR_3E # !RST;
PORT_3E_B5 = PORT_3E_B5 & !WR_3E # D5 & WR_3E # !RST;
PORT_3E_B4 = PORT_3E_B4 & !WR_3E & RST # D4 & WR_3E;
PORT_3E_B3 = PORT_3E_B3 & !WR_3E & RST # D3 & WR_3E;
PORT_3E_B2 = PORT_3E_B2 & !WR_3E & RST # D2 & WR_3E;
PORT_3E_B1 = PORT_3E_B1 & !WR_3E & RST # D1 & WR_3E;
PORT_3E_B0 = PORT_3E_B0 & !WR_3E & RST # D0 & WR_3E;

!CE4 = !PORT_3E_B7 & !MREQ; /* EXT */
!CE3 = !PORT_3E_B6 & !MREQ; /* CART */
!CE2 = !PORT_3E_B5 & !MREQ; /* CARD */
!CE1 = !PORT_3E_B4 & !CSRAM; /* RAM */
!CE0 = !PORT_3E_B3 & !MREQ; /* BIOS */

/* PORT $3F */
/* Init = 0xFF */

WR_3F = !A7 & !A6 & A0 & !WR & !IOREQ & !KILLGA;

PORT_3F = PORT_3F & !WR_3F # DATA & WR_3F # !RST;

TH2.oe = !PORT_3F_B3;
TR2.oe = !PORT_3F_B2;
TH1.oe = !PORT_3F_B1;
TR1.oe = !PORT_3F_B0;
TH2 = PORT_3F_B7;
TR2 = PORT_3F_B6;
TH1 = PORT_3F_B5;
TR1 = PORT_3F_B4;

/* PORTS $DC & $DD */

DATA.oe = A7 & A6 & !RD & !IOREQ & !KILLGA & !PORT_3E_B2;
DATA = PORT_DC & !A0 # PORT_DD & A0;

/* HL */
!HL = (!TH1.oe & !TH1 # !TH2.oe & !TH2);

Also to be noted, some resistors are needed (measured to be around 5kΩ):
- pull-ups on all controllers inputs
- pull-down on !KILLGA

[EDIT] jed file recompiled and attached
[EDIT 2] gerbers attached

20230807_170033.jpg (3.5 MB)

20230807_165921.jpg (3.61 MB)

20230807_165941.jpg (3.46 MB)

315-5216.PNG (68.16 KB)

315-5216 (gerbers).zip (21.56 KB)

315-5216 (JED).zip (2.91 KB)

315-5237

Some corrections to the information there:
https://www.smspower.org/forums/7981-3155237TechnicalLong
- Pin 40 is GND (connected internally to pin 24) and probably used as a shield for clock signals
- Pin 44 (!SYNC) is an output
- Pin 45 (PALALT) is an input

Rest has been confirmed by asynchronous already (pin 33 = CONT1 = reset button, pin 35 = CE4, pin 37 = CE2) but not updated in first post.

Contrary to what was expected pin 42 (SC) is always MCLK/12, making the 315-5237 PAL only.

The 315-5237 is just a 315-5216 with a few extra functions:
- when !RST_IN (pin 47) goes low, !RST_OUT (pin 46), DIV5 (pin 41), DIV12 (pin 42) and PALALT (pin 45) go low on the next MCLK rising edge
- reset signal filtering: !RST_OUT is !RST_IN delayed 40 clock cycles
- 2 clock dividers, pin 41 is MCLK divided by 5 delayed 2 clock cycles and with a 3/5 duty cycle, pin 42 is MCK divided by 12 delayed 3 clock cycles with a 50% duty cycle, which gives the following chronogram:

CYCLE 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728
MCLK (pin 43) HLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHL
DIV5 (pin 41) LLLLHHHHHHLLLLHHHHHHLLLLHHHHHHLLLLHHHHHHLLLLHHHHHHLLLLHH
DIV12 (pin 42) LLLLLLHHHHHHHHHHHHLLLLLLLLLLLLHHHHHHHHHHHHLLLLLLLLLLLLHH

- PALALT changes state (initial = low) on every !SYNC rising edge (divided by 2)

Name 315-5237;
PartNo 00;
Date 23/07/2019;
Revision 01;
Designer Apocalypse;
Company PC;
Assembly None;
Location ;
Device f1504ispplcc84;

PROPERTY ATMEL {TDI_pullup = ON};
PROPERTY ATMEL {TMS_pullup = ON};
PROPERTY ATMEL {power_reset= ON};

/****************************************************************/
/* */
/* General File Comments */
/* */
/****************************************************************/

/*
* Pins: define pins in this section
*/

Pin 4 = CE0; /* 39 - O */
Pin 5 = CE1; /* 38 - O */
Pin 6 = CE2; /* 37 - O */
Pin 8 = CE3; /* 36 - O */
Pin 9 = CE4; /* 35 - O */
Pin 10 = D0; /* 32 - IO */
Pin 11 = D1; /* 31 - IO */
Pin 12 = D2; /* 30 - IO */
/* Pin 14 = TDI */
Pin 15 = D3; /* 29 - IO */
Pin 16 = D4; /* 28 - IO */
Pin 17 = D5; /* 27 - IO */
Pin 18 = D6; /* 26 - IO */
Pin 21 = D7; /* 25 - IO */
Pin 22 = A0; /* 2 - I */
/* Pin 23 = TMS */
Pin 24 = A6; /* 3 - I */
Pin 25 = A7; /* 4 - I */
Pin 27 = MREQ; /* 8 - I */
Pin 28 = IOREQ; /* 7 - I */
Pin 29 = RD; /* 6 - I */
Pin 30 = WR; /* 5 - I */
Pin 31 = CONT1; /* 33 - I */
Pin 33 = KILLGA; /* 1 - I */
Pin 34 = CSRAM; /* 9 - I */
Pin 35 = UP1; /* 10 - I */
Pin 36 = DN1; /* 11 - I */
Pin 37 = LE1; /* 12 - I */
Pin 39 = RI1; /* 13 - I */
Pin 40 = TL1; /* 14 - I */
Pin 41 = TR1; /* 20 - IO */
Pin 44 = TH1; /* 21 - IO */
Pin 45 = HL; /* 34 - O */
Pin 48 = TH2; /* 23 - IO */
Pin 49 = TR2; /* 22 - IO */
Pin 50 = TL2; /* 19 - I */
Pin 51 = RI2; /* 18 - I */
Pin 52 = LE2; /* 17 - I */
Pin 54 = DN2; /* 16 - I */
Pin 55 = UP2; /* 15 - I */
Pin 56 = RST; /* 47 - I */
/*Pin 57 = CONT2;*/ /* NC - I */
Pin 58 = MCLK_DIV_5; /* 41 - O */
Pin 60 = MCLK_DIV_12;/* 42 - O */
Pin 61 = MCLK; /* 43 - I */
/* Pin 62 = TCK */
Pin 63 = PALALT; /* 44 - O */
Pin 64 = SYNC; /* 45 - I */
Pin 65 = RST_OUT; /* 46 - O */
/* Pin 71 = TDO */

/*
* Nodes: define nodes as active HI levels in this section
*/

Node [PORT_3E_B7..0];
Node [PORT_3F_B7..0];
Node [DIV5_CNT2..0];
Node [DIV12_CNT3..0];
Node [RST_CNT5..0];

Node WR_3E;
Node WR_3F;

/*
* Fields: define fields in this section
*/

Field PORT_3E = [PORT_3E_B7..0];
Field PORT_3F = [PORT_3F_B7..0];
Field PORT_DC = [DN2,UP2,TR1,TL1,RI1,LE1,DN1,UP1];
/*Field PORT_DD = [TH2,TH1,CONT2,CONT1,TR2,TL2,RI2,LE2];*/
Field PORT_DD = [TH2,TH1,'b'1,CONT1,TR2,TL2,RI2,LE2];
Field DATA = [D7..0];
Field DIV5_COUNT = [DIV5_CNT2..0];
Field DIV12_COUNT = [DIV12_CNT3..0];
Field RST_COUNT = [RST_CNT5..0];

/*
* Logic: logic equations in this section
*/

/* PORT $3E */
/* Init = 0xE0 */

WR_3E = !A7 & !A6 & !A0 & !WR & !IOREQ & !KILLGA;

PORT_3E_B7 = PORT_3E_B7 & !WR_3E # D7 & WR_3E # !RST;
PORT_3E_B6 = PORT_3E_B6 & !WR_3E # D6 & WR_3E # !RST;
PORT_3E_B5 = PORT_3E_B5 & !WR_3E # D5 & WR_3E # !RST;
PORT_3E_B4 = PORT_3E_B4 & !WR_3E & RST # D4 & WR_3E;
PORT_3E_B3 = PORT_3E_B3 & !WR_3E & RST # D3 & WR_3E;
PORT_3E_B2 = PORT_3E_B2 & !WR_3E & RST # D2 & WR_3E;
PORT_3E_B1 = PORT_3E_B1 & !WR_3E & RST # D1 & WR_3E;
PORT_3E_B0 = PORT_3E_B0 & !WR_3E & RST # D0 & WR_3E;

!CE4 = !PORT_3E_B7 & !MREQ; /* EXT */
!CE3 = !PORT_3E_B6 & !MREQ; /* CART */
!CE2 = !PORT_3E_B5 & !MREQ; /* CARD */
!CE1 = !PORT_3E_B4 & !CSRAM; /* RAM */
!CE0 = !PORT_3E_B3 & !MREQ; /* BIOS */

/* PORT $3F */
/* Init = 0xFF */

WR_3F = !A7 & !A6 & A0 & !WR & !IOREQ & !KILLGA;

PORT_3F = PORT_3F & !WR_3F # DATA & WR_3F # !RST;

TH2.oe = !PORT_3F_B3;
TR2.oe = !PORT_3F_B2;
TH1.oe = !PORT_3F_B1;
TR1.oe = !PORT_3F_B0;
TH2 = PORT_3F_B7;
TR2 = PORT_3F_B6;
TH1 = PORT_3F_B5;
TR1 = PORT_3F_B4;

/* PORTS $DC & $DD */

DATA.oe = A7 & A6 & !RD & !IOREQ & !KILLGA & !PORT_3E_B2;
DATA = PORT_DC & !A0 # PORT_DD & A0;

/* HL */
!HL = (!TH1.oe & !TH1 # !TH2.oe & !TH2);

/* PALALT */
PALALT.ar = !RST & MCLK;
PALALT.ck = SYNC;
PALALT.d = !PALALT;

/* CLOCKS */

/* MCLK divided by 5, delayed 2 MCLK cycles, 3/5 duty cycle */

/* 3 bit counter 0x00 - 0x04 */
DIV5_COUNT.ar = !RST & MCLK;
DIV5_COUNT.ck = MCLK;
DIV5_CNT2.d = !(DIV5_CNT2 & !DIV5_CNT1 & !DIV5_CNT0) & (!DIV5_CNT2 & DIV5_CNT1 & DIV5_CNT0 # DIV5_CNT2 & !(DIV5_CNT1 & DIV5_CNT0));
DIV5_CNT1.d = !(DIV5_CNT2 & !DIV5_CNT1 & !DIV5_CNT0) & (!DIV5_CNT1 & DIV5_CNT0 # DIV5_CNT1 & !DIV5_CNT0);
DIV5_CNT0.d = !(DIV5_CNT2 & !DIV5_CNT1 & !DIV5_CNT0) & !DIV5_CNT0;

MCLK_DIV_5 = DIV5_CNT2 # DIV5_CNT1;

/* MCLK divided by 12, delayed 3 MCLK cycles, 50% duty cycle */

/* 4 bit counter 0x00 - 0x0B */
DIV12_COUNT.ar = !RST & MCLK;
DIV12_COUNT.ck = MCLK;
DIV12_CNT3.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & (!DIV12_CNT3 & DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT3 & !(DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0));
DIV12_CNT2.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & (!DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT2 & !(DIV12_CNT1 & DIV12_CNT0));
DIV12_CNT1.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & (!DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT1 & !DIV12_CNT0);
DIV12_CNT0.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & !DIV12_CNT0;

MCLK_DIV_12 = DIV12_CNT2 # !DIV12_CNT3 & DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT3 & !DIV12_CNT1 & !DIV12_CNT0;

/* RESET - delayed 40 MCLK cycles */

/* 6 bit counter - simplified as we only need to count up to 0x27 (no rollback at 0x27 or past 0x3F) */
RST_COUNT.ar = !RST & MCLK;
RST_COUNT.ck = MCLK;
RST_CNT5.d = !RST_CNT5 & RST_CNT4 & RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT5;
RST_CNT4.d = !RST_CNT4 & RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT4 & !(RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0);
RST_CNT3.d = !RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT3 & !(RST_CNT2 & RST_CNT1 & RST_CNT0);
RST_CNT2.d = !RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT2 & !(RST_CNT1 & RST_CNT0);
RST_CNT1.d = !RST_CNT1 & RST_CNT0 # RST_CNT1 & !RST_CNT0;
RST_CNT0.d = !RST_CNT0;

RST_OUT.ar = !RST & MCLK;
RST_OUT.ck = RST_CNT5 & !RST_CNT4 & !RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0; /* 0x27 */
RST_OUT.d = RST;

[EDIT] jed file recompiled and attached
[EDIT 2] gerbers also attached

315-5237.PNG (53.31 KB)

315-5237 (gerbers).zip (25.97 KB)

315-5237 (JED).zip (3.7 KB)

315-5297

I realise we're also missing the I/O chip found only in Japanese Master System consoles:
https://www.smspower.org/forums/15109-3155297AndMoreJapaneseMSStuffPinout

I unfortunately don't own one, if someone wants to donate a working chip to the cause I'll reverse it (though pretty much everything is known/can be guessed at this point).

Apocalypse wrote

315-5297

I realise we're also missing the I/O chip found only in Japanese Master System consoles:
https://www.smspower.org/forums/15109-3155297AndMoreJapaneseMSStuffPinout

I unfortunately don't own one, if someone wants to donate a working chip to the cause I'll reverse it (though pretty much everything is known/can be guessed at this point).

Is this a replacement of the custom SMS chip? I guess is because could be fault and is not available anymore...

Use [code][/code] tags to get monospaced.

siriokds wrote

Is this a replacement of the custom SMS chip? I guess is because could be fault and is not available anymore...

Yes the goal is to be able to make replacements and repair faulty consoles.

Maxim wrote

Use
tags to get monospaced.

Done, thanks.

ATF1504AS-15JC84 will work, or does it needs a faster one?

The following is needed for 315-5297, too?
"Also to be noted, some resistors are needed (measured to be around 5kΩ):
- pull-ups on all controllers inputs
- pull-down on !KILLGA "

pin 84 (i/OE1) of atf1504 should be left floating or grounded? The same question for pin 2 OE2/I

I haven't tested with 15ns devices but that should be plenty fast for the old 3.58MHz SMS.
I have gerbers somewhere for the 315-5216 and 315-5237 but footprints are too big for my liking (see pictures of the 315-5216 above), I'd rather switch fully to SMT and use a much smaller QFP100 chip.

315-5297 I haven't reversed yet, I'm looking for a working chip.

To be clear you need pull-ups on:
- UP1
- DN1
- LE1
- RI1
- TL1
- TR1
- TH1
- UP2
- DN2
- LE2
- RI2
- TL2
- TR2
- TH2
- CONT1 (reset switch, hardwired to Vcc on SMS2)
- CONT2 (doesn't exists on the 315-5237)

And a pull-down on KILLGA.

Unused pins can be left floating (there are "weak" pull-up resistors inside the CPLD of around 50kΩ), you don't need to worry about dedicated OE signals, their usage is defined in the jed file, in our case they are not used.

Thank you for your answer.
My mistake. Bad typing. I meant 315-5237, for sms2.
And I understand now. The pullups and the one pulldown are required for all replacements chips.
Another question if you don't mind. I'm confused about a few more pins in 315-5237. There's a difference between the ones you posted and the ones in the link you provided:

YOURS LINK
45-SYNC | GND
46-nothing | RST
47-RST | POR
48-RST_OUT | VCC

I've uploaded the jed files and gerbers.

C1 = 100nF ceramic
R1 = 4.7K
RA1/RA2 = resistor array network (8R) 4.7K

45-SYNC | GND
46-nothing | RST
47-RST | POR
48-RST_OUT | VCC

There was a mistake in the comment for RST_OUT, it is indeed pin 46.
45 is named !SYNC from the schematics. As explained the pinout wasn't complete in the other thread, that pin (along with PALALT) aren't used but I still implemented them in the repro for the sake of completeness.

Thank you for your hard work!
Since I'm new to this, the gerber and the jed are very helpful.
I will order the parts and post back in a couple of months when they arrive.

Hello,

@furrtek has now decapped the 315-5216 chip and found a small difference with my repro based on signal analysis: the KILLGA signal also disables writes to ports $3E and $3F.

https://github.com/furrtek/SiliconRE/tree/master/Sega/315-5216

This is now fixed in the equations and jed files above, many thanks to him for the feedback.

Author	Message
Apocalypse Joined: 26 Feb 2021 Posts: 163	315-5216 and 315-5237 I/O chips reproductions (also looking for a 315-5297 chip) Posted: Sun Aug 06, 2023 10:01 am Last edited by Apocalypse on Tue Aug 08, 2023 10:41 pm; edited 3 times in total
Apocalypse Joined: 26 Feb 2021 Posts: 163	Those are the I/O chips (plus a few other functions) found in Master System consoles. I reversed them and even tested repros in CPLDs some years ago, following a repair I had made on a MS2 with a partially faulty 315-5237 (some inputs were stuck low = buttons seen as pressed). After reading a message from @willbritton on Discord I decided to document my work better (I'm terrible at documenting things...). Following two posts, one for each chip.

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Sun Aug 06, 2023 10:01 am Last edited by Apocalypse on Fri Aug 02, 2024 9:34 pm; edited 16 times in total
Apocalypse Joined: 26 Feb 2021 Posts: 163	315-5216 First, there are some mistakes there: https://www.smspower.org/Development/IOCtrlPinouts - pin 22 is connected to the reset button on MS1 - !KILLGA (pin 23) & !CSRAM (pin 24) are both inputs The equations: I always start my designs using either an ATF1508 or an EPM7128 in PLCC84 for their high number of I/Os and macrocells, then once I reach a working design I try to find the smallest device it could fit in (both in terms of I/Os and macrocells). In that case an ATF1504/EPM7064 is enough, 40 I/Os are needed which discards the 44 pin devices, 68 pin ones are pretty much unobtainable, the nice and small TQFP100s are expensive, so I sticked to the "big" PLCC84 version. I'll try to post a picture of the repro PCB, it's not the best aesthetically... Feel free to adapt the code below to your targeted chip of choice. [EDIT] I've declared two more nodes to reduce drastically macrocell count. Now requires only 32. Name 315-5216; PartNo 00; Date 12/06/2019; Revision 01; Designer Apocalypse; Company PC; Assembly None; Location ; Device f1504ispplcc84; PROPERTY ATMEL {TDI_pullup = ON}; PROPERTY ATMEL {TMS_pullup = ON}; PROPERTY ATMEL {power_reset= ON}; /***************************************************************/ / / / General File Comments / / / /**************************************************************/ / * Pins: define pins in this section / Pin 4 = CE0; / 1 - O / Pin 5 = CE1; / 2 - O / Pin 6 = CE2; / 3 - O / Pin 8 = CE3; / 4 - O / Pin 9 = CE4; / 5 - O / Pin 10 = D0; / 6 - IO / Pin 11 = D1; / 7 - IO / Pin 12 = D2; / 8 - IO / / Pin 14 = TDI / Pin 15 = D3; / 9 - IO / Pin 16 = D4; / 10 - IO / Pin 17 = D5; / 12 - IO / Pin 18 = D6; / 13 - IO / Pin 21 = D7; / 14 - IO / Pin 22 = A0; / 15 - I / / Pin 23 = TMS / Pin 24 = A6; / 16 - I / Pin 25 = A7; / 17 - I / Pin 27 = MREQ; / 18 - I / Pin 28 = IOREQ; / 19 - I / Pin 29 = RD; / 20 - I / Pin 30 = WR; / 21 - I / Pin 31 = CONT1; / 22 - I / Pin 33 = KILLGA; / 23 - I / Pin 34 = CSRAM; / 24 - I / Pin 35 = UP1; / 25 - I / Pin 36 = DN1; / 26 - I / Pin 37 = LE1; / 27 - I / Pin 39 = RI1; / 28 - I / Pin 40 = TL1; / 29 - I / Pin 41 = TR1; / 30 - IO / Pin 44 = TH1; / 31 - IO / Pin 45 = HL; / 33 - O / Pin 48 = TH2; / 34 - IO / Pin 49 = TR2; / 35 - IO / Pin 50 = TL2; / 36 - I / Pin 51 = RI2; / 37 - I / Pin 52 = LE2; / 38 - I / Pin 54 = DN2; / 39 - I / Pin 55 = UP2; / 40 - I / Pin 56 = RST; / 41 - I / Pin 57 = CONT2; / 42 - I / / Pin 62 = TCK / / Pin 71 = TDO / / * Nodes: define nodes as active HI levels in this section / Node [PORT_3E_B7..0]; Node [PORT_3F_B7..0]; Node WR_3E; Node WR_3F; / * Fields: define fields in this section / Field PORT_3E = [PORT_3E_B7..0]; Field PORT_3F = [PORT_3F_B7..0]; Field PORT_DC = [DN2,UP2,TR1,TL1,RI1,LE1,DN1,UP1]; Field PORT_DD = [TH2,TH1,CONT2,CONT1,TR2,TL2,RI2,LE2]; Field DATA = [D7..0]; / * Logic: logic equations in this section / / PORT $3E / / Init = 0xE0 / WR_3E = !A7 & !A6 & !A0 & !WR & !IOREQ & !KILLGA; PORT_3E_B7 = PORT_3E_B7 & !WR_3E # D7 & WR_3E # !RST; PORT_3E_B6 = PORT_3E_B6 & !WR_3E # D6 & WR_3E # !RST; PORT_3E_B5 = PORT_3E_B5 & !WR_3E # D5 & WR_3E # !RST; PORT_3E_B4 = PORT_3E_B4 & !WR_3E & RST # D4 & WR_3E; PORT_3E_B3 = PORT_3E_B3 & !WR_3E & RST # D3 & WR_3E; PORT_3E_B2 = PORT_3E_B2 & !WR_3E & RST # D2 & WR_3E; PORT_3E_B1 = PORT_3E_B1 & !WR_3E & RST # D1 & WR_3E; PORT_3E_B0 = PORT_3E_B0 & !WR_3E & RST # D0 & WR_3E; !CE4 = !PORT_3E_B7 & !MREQ; / EXT / !CE3 = !PORT_3E_B6 & !MREQ; / CART / !CE2 = !PORT_3E_B5 & !MREQ; / CARD / !CE1 = !PORT_3E_B4 & !CSRAM; / RAM / !CE0 = !PORT_3E_B3 & !MREQ; / BIOS / / PORT $3F / / Init = 0xFF / WR_3F = !A7 & !A6 & A0 & !WR & !IOREQ & !KILLGA; PORT_3F = PORT_3F & !WR_3F # DATA & WR_3F # !RST; TH2.oe = !PORT_3F_B3; TR2.oe = !PORT_3F_B2; TH1.oe = !PORT_3F_B1; TR1.oe = !PORT_3F_B0; TH2 = PORT_3F_B7; TR2 = PORT_3F_B6; TH1 = PORT_3F_B5; TR1 = PORT_3F_B4; / PORTS $DC & $DD / DATA.oe = A7 & A6 & !RD & !IOREQ & !KILLGA & !PORT_3E_B2; DATA = PORT_DC & !A0 # PORT_DD & A0; / HL */ !HL = (!TH1.oe & !TH1 # !TH2.oe & !TH2); Also to be noted, some resistors are needed (measured to be around 5kΩ): - pull-ups on all controllers inputs - pull-down on !KILLGA [EDIT] jed file recompiled and attached [EDIT 2] gerbers attached 20230807_170033.jpg (3.5 MB) 20230807_165921.jpg (3.61 MB) 20230807_165941.jpg (3.46 MB) 315-5216.PNG (68.16 KB) 315-5216 (gerbers).zip (21.56 KB) 315-5216 (JED).zip (2.91 KB)

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Sun Aug 06, 2023 10:02 am Last edited by Apocalypse on Fri Aug 02, 2024 9:36 pm; edited 7 times in total
Apocalypse Joined: 26 Feb 2021 Posts: 163	315-5237 Some corrections to the information there: https://www.smspower.org/forums/7981-3155237TechnicalLong - Pin 40 is GND (connected internally to pin 24) and probably used as a shield for clock signals - Pin 44 (!SYNC) is an output - Pin 45 (PALALT) is an input Rest has been confirmed by asynchronous already (pin 33 = CONT1 = reset button, pin 35 = CE4, pin 37 = CE2) but not updated in first post. Contrary to what was expected pin 42 (SC) is always MCLK/12, making the 315-5237 PAL only. The 315-5237 is just a 315-5216 with a few extra functions: - when !RST_IN (pin 47) goes low, !RST_OUT (pin 46), DIV5 (pin 41), DIV12 (pin 42) and PALALT (pin 45) go low on the next MCLK rising edge - reset signal filtering: !RST_OUT is !RST_IN delayed 40 clock cycles - 2 clock dividers, pin 41 is MCLK divided by 5 delayed 2 clock cycles and with a 3/5 duty cycle, pin 42 is MCK divided by 12 delayed 3 clock cycles with a 50% duty cycle, which gives the following chronogram: CYCLE 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728 MCLK (pin 43) HLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHLHL DIV5 (pin 41) LLLLHHHHHHLLLLHHHHHHLLLLHHHHHHLLLLHHHHHHLLLLHHHHHHLLLLHH DIV12 (pin 42) LLLLLLHHHHHHHHHHHHLLLLLLLLLLLLHHHHHHHHHHHHLLLLLLLLLLLLHH - PALALT changes state (initial = low) on every !SYNC rising edge (divided by 2) Name 315-5237; PartNo 00; Date 23/07/2019; Revision 01; Designer Apocalypse; Company PC; Assembly None; Location ; Device f1504ispplcc84; PROPERTY ATMEL {TDI_pullup = ON}; PROPERTY ATMEL {TMS_pullup = ON}; PROPERTY ATMEL {power_reset= ON}; /***************************************************************/ / / / General File Comments / / / /**************************************************************/ / * Pins: define pins in this section / Pin 4 = CE0; / 39 - O / Pin 5 = CE1; / 38 - O / Pin 6 = CE2; / 37 - O / Pin 8 = CE3; / 36 - O / Pin 9 = CE4; / 35 - O / Pin 10 = D0; / 32 - IO / Pin 11 = D1; / 31 - IO / Pin 12 = D2; / 30 - IO / / Pin 14 = TDI / Pin 15 = D3; / 29 - IO / Pin 16 = D4; / 28 - IO / Pin 17 = D5; / 27 - IO / Pin 18 = D6; / 26 - IO / Pin 21 = D7; / 25 - IO / Pin 22 = A0; / 2 - I / / Pin 23 = TMS / Pin 24 = A6; / 3 - I / Pin 25 = A7; / 4 - I / Pin 27 = MREQ; / 8 - I / Pin 28 = IOREQ; / 7 - I / Pin 29 = RD; / 6 - I / Pin 30 = WR; / 5 - I / Pin 31 = CONT1; / 33 - I / Pin 33 = KILLGA; / 1 - I / Pin 34 = CSRAM; / 9 - I / Pin 35 = UP1; / 10 - I / Pin 36 = DN1; / 11 - I / Pin 37 = LE1; / 12 - I / Pin 39 = RI1; / 13 - I / Pin 40 = TL1; / 14 - I / Pin 41 = TR1; / 20 - IO / Pin 44 = TH1; / 21 - IO / Pin 45 = HL; / 34 - O / Pin 48 = TH2; / 23 - IO / Pin 49 = TR2; / 22 - IO / Pin 50 = TL2; / 19 - I / Pin 51 = RI2; / 18 - I / Pin 52 = LE2; / 17 - I / Pin 54 = DN2; / 16 - I / Pin 55 = UP2; / 15 - I / Pin 56 = RST; / 47 - I / /Pin 57 = CONT2;/ / NC - I / Pin 58 = MCLK_DIV_5; / 41 - O / Pin 60 = MCLK_DIV_12;/ 42 - O / Pin 61 = MCLK; / 43 - I / / Pin 62 = TCK / Pin 63 = PALALT; / 44 - O / Pin 64 = SYNC; / 45 - I / Pin 65 = RST_OUT; / 46 - O / / Pin 71 = TDO / / * Nodes: define nodes as active HI levels in this section / Node [PORT_3E_B7..0]; Node [PORT_3F_B7..0]; Node [DIV5_CNT2..0]; Node [DIV12_CNT3..0]; Node [RST_CNT5..0]; Node WR_3E; Node WR_3F; / * Fields: define fields in this section / Field PORT_3E = [PORT_3E_B7..0]; Field PORT_3F = [PORT_3F_B7..0]; Field PORT_DC = [DN2,UP2,TR1,TL1,RI1,LE1,DN1,UP1]; /Field PORT_DD = [TH2,TH1,CONT2,CONT1,TR2,TL2,RI2,LE2];/ Field PORT_DD = [TH2,TH1,'b'1,CONT1,TR2,TL2,RI2,LE2]; Field DATA = [D7..0]; Field DIV5_COUNT = [DIV5_CNT2..0]; Field DIV12_COUNT = [DIV12_CNT3..0]; Field RST_COUNT = [RST_CNT5..0]; / * Logic: logic equations in this section / / PORT $3E / / Init = 0xE0 / WR_3E = !A7 & !A6 & !A0 & !WR & !IOREQ & !KILLGA; PORT_3E_B7 = PORT_3E_B7 & !WR_3E # D7 & WR_3E # !RST; PORT_3E_B6 = PORT_3E_B6 & !WR_3E # D6 & WR_3E # !RST; PORT_3E_B5 = PORT_3E_B5 & !WR_3E # D5 & WR_3E # !RST; PORT_3E_B4 = PORT_3E_B4 & !WR_3E & RST # D4 & WR_3E; PORT_3E_B3 = PORT_3E_B3 & !WR_3E & RST # D3 & WR_3E; PORT_3E_B2 = PORT_3E_B2 & !WR_3E & RST # D2 & WR_3E; PORT_3E_B1 = PORT_3E_B1 & !WR_3E & RST # D1 & WR_3E; PORT_3E_B0 = PORT_3E_B0 & !WR_3E & RST # D0 & WR_3E; !CE4 = !PORT_3E_B7 & !MREQ; / EXT / !CE3 = !PORT_3E_B6 & !MREQ; / CART / !CE2 = !PORT_3E_B5 & !MREQ; / CARD / !CE1 = !PORT_3E_B4 & !CSRAM; / RAM / !CE0 = !PORT_3E_B3 & !MREQ; / BIOS / / PORT $3F / / Init = 0xFF / WR_3F = !A7 & !A6 & A0 & !WR & !IOREQ & !KILLGA; PORT_3F = PORT_3F & !WR_3F # DATA & WR_3F # !RST; TH2.oe = !PORT_3F_B3; TR2.oe = !PORT_3F_B2; TH1.oe = !PORT_3F_B1; TR1.oe = !PORT_3F_B0; TH2 = PORT_3F_B7; TR2 = PORT_3F_B6; TH1 = PORT_3F_B5; TR1 = PORT_3F_B4; / PORTS $DC & $DD / DATA.oe = A7 & A6 & !RD & !IOREQ & !KILLGA & !PORT_3E_B2; DATA = PORT_DC & !A0 # PORT_DD & A0; / HL / !HL = (!TH1.oe & !TH1 # !TH2.oe & !TH2); / PALALT / PALALT.ar = !RST & MCLK; PALALT.ck = SYNC; PALALT.d = !PALALT; / CLOCKS / / MCLK divided by 5, delayed 2 MCLK cycles, 3/5 duty cycle / / 3 bit counter 0x00 - 0x04 / DIV5_COUNT.ar = !RST & MCLK; DIV5_COUNT.ck = MCLK; DIV5_CNT2.d = !(DIV5_CNT2 & !DIV5_CNT1 & !DIV5_CNT0) & (!DIV5_CNT2 & DIV5_CNT1 & DIV5_CNT0 # DIV5_CNT2 & !(DIV5_CNT1 & DIV5_CNT0)); DIV5_CNT1.d = !(DIV5_CNT2 & !DIV5_CNT1 & !DIV5_CNT0) & (!DIV5_CNT1 & DIV5_CNT0 # DIV5_CNT1 & !DIV5_CNT0); DIV5_CNT0.d = !(DIV5_CNT2 & !DIV5_CNT1 & !DIV5_CNT0) & !DIV5_CNT0; MCLK_DIV_5 = DIV5_CNT2 # DIV5_CNT1; / MCLK divided by 12, delayed 3 MCLK cycles, 50% duty cycle / / 4 bit counter 0x00 - 0x0B / DIV12_COUNT.ar = !RST & MCLK; DIV12_COUNT.ck = MCLK; DIV12_CNT3.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & (!DIV12_CNT3 & DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT3 & !(DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0)); DIV12_CNT2.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & (!DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT2 & !(DIV12_CNT1 & DIV12_CNT0)); DIV12_CNT1.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & (!DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT1 & !DIV12_CNT0); DIV12_CNT0.d = !(DIV12_CNT3 & !DIV12_CNT2 & DIV12_CNT1 & DIV12_CNT0) & !DIV12_CNT0; MCLK_DIV_12 = DIV12_CNT2 # !DIV12_CNT3 & DIV12_CNT1 & DIV12_CNT0 # DIV12_CNT3 & !DIV12_CNT1 & !DIV12_CNT0; / RESET - delayed 40 MCLK cycles / / 6 bit counter - simplified as we only need to count up to 0x27 (no rollback at 0x27 or past 0x3F) / RST_COUNT.ar = !RST & MCLK; RST_COUNT.ck = MCLK; RST_CNT5.d = !RST_CNT5 & RST_CNT4 & RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT5; RST_CNT4.d = !RST_CNT4 & RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT4 & !(RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0); RST_CNT3.d = !RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT3 & !(RST_CNT2 & RST_CNT1 & RST_CNT0); RST_CNT2.d = !RST_CNT2 & RST_CNT1 & RST_CNT0 # RST_CNT2 & !(RST_CNT1 & RST_CNT0); RST_CNT1.d = !RST_CNT1 & RST_CNT0 # RST_CNT1 & !RST_CNT0; RST_CNT0.d = !RST_CNT0; RST_OUT.ar = !RST & MCLK; RST_OUT.ck = RST_CNT5 & !RST_CNT4 & !RST_CNT3 & RST_CNT2 & RST_CNT1 & RST_CNT0; / 0x27 */ RST_OUT.d = RST; [EDIT] jed file recompiled and attached [EDIT 2] gerbers also attached 315-5237.PNG (53.31 KB) 315-5237 (gerbers).zip (25.97 KB) 315-5237 (JED).zip (3.7 KB)

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Tue Aug 08, 2023 10:40 pm
Apocalypse Joined: 26 Feb 2021 Posts: 163	315-5297 I realise we're also missing the I/O chip found only in Japanese Master System consoles: https://www.smspower.org/forums/15109-3155297AndMoreJapaneseMSStuffPinout I unfortunately don't own one, if someone wants to donate a working chip to the cause I'll reverse it (though pretty much everything is known/can be guessed at this point).

siriokds Joined: 10 Dec 2009 Posts: 118	Posted: Wed Aug 09, 2023 5:57 am
siriokds Joined: 10 Dec 2009 Posts: 118	Apocalypse wrote 315-5297 I realise we're also missing the I/O chip found only in Japanese Master System consoles: https://www.smspower.org/forums/15109-3155297AndMoreJapaneseMSStuffPinout I unfortunately don't own one, if someone wants to donate a working chip to the cause I'll reverse it (though pretty much everything is known/can be guessed at this point). Is this a replacement of the custom SMS chip? I guess is because could be fault and is not available anymore...

Maxim Site Admin Joined: 19 Oct 1999 Posts: 14937 Location: London	Posted: Wed Aug 09, 2023 6:19 am
	Use [code][/code] tags to get monospaced.

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Wed Aug 09, 2023 9:08 pm
Apocalypse Joined: 26 Feb 2021 Posts: 163	siriokds wrote Is this a replacement of the custom SMS chip? I guess is because could be fault and is not available anymore... Yes the goal is to be able to make replacements and repair faulty consoles. Maxim wrote Use tags to get monospaced. Done, thanks.

gorgyrip Joined: 11 Mar 2006 Posts: 81	Posted: Sun Aug 13, 2023 4:39 pm
gorgyrip Joined: 11 Mar 2006 Posts: 81	ATF1504AS-15JC84 will work, or does it needs a faster one? The following is needed for 315-5297, too? "Also to be noted, some resistors are needed (measured to be around 5kΩ): - pull-ups on all controllers inputs - pull-down on !KILLGA " pin 84 (i/OE1) of atf1504 should be left floating or grounded? The same question for pin 2 OE2/I

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Sun Aug 13, 2023 11:21 pm
Apocalypse Joined: 26 Feb 2021 Posts: 163	I haven't tested with 15ns devices but that should be plenty fast for the old 3.58MHz SMS. I have gerbers somewhere for the 315-5216 and 315-5237 but footprints are too big for my liking (see pictures of the 315-5216 above), I'd rather switch fully to SMT and use a much smaller QFP100 chip. 315-5297 I haven't reversed yet, I'm looking for a working chip. To be clear you need pull-ups on: - UP1 - DN1 - LE1 - RI1 - TL1 - TR1 - TH1 - UP2 - DN2 - LE2 - RI2 - TL2 - TR2 - TH2 - CONT1 (reset switch, hardwired to Vcc on SMS2) - CONT2 (doesn't exists on the 315-5237) And a pull-down on KILLGA. Unused pins can be left floating (there are "weak" pull-up resistors inside the CPLD of around 50kΩ), you don't need to worry about dedicated OE signals, their usage is defined in the jed file, in our case they are not used.

gorgyrip Joined: 11 Mar 2006 Posts: 81	Posted: Sun Aug 13, 2023 11:53 pm
gorgyrip Joined: 11 Mar 2006 Posts: 81	Thank you for your answer. My mistake. Bad typing. I meant 315-5237, for sms2. And I understand now. The pullups and the one pulldown are required for all replacements chips. Another question if you don't mind. I'm confused about a few more pins in 315-5237. There's a difference between the ones you posted and the ones in the link you provided: YOURS LINK 45-SYNC \| GND 46-nothing \| RST 47-RST \| POR 48-RST_OUT \| VCC

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Mon Aug 14, 2023 12:07 am
Apocalypse Joined: 26 Feb 2021 Posts: 163	I've uploaded the jed files and gerbers. C1 = 100nF ceramic R1 = 4.7K RA1/RA2 = resistor array network (8R) 4.7K 45-SYNC \| GND 46-nothing \| RST 47-RST \| POR 48-RST_OUT \| VCC There was a mistake in the comment for RST_OUT, it is indeed pin 46. 45 is named !SYNC from the schematics. As explained the pinout wasn't complete in the other thread, that pin (along with PALALT) aren't used but I still implemented them in the repro for the sake of completeness.

gorgyrip Joined: 11 Mar 2006 Posts: 81	Posted: Mon Aug 14, 2023 9:44 am
gorgyrip Joined: 11 Mar 2006 Posts: 81	Thank you for your hard work! Since I'm new to this, the gerber and the jed are very helpful. I will order the parts and post back in a couple of months when they arrive.

Apocalypse Joined: 26 Feb 2021 Posts: 163	Posted: Fri Aug 02, 2024 9:38 pm
Apocalypse Joined: 26 Feb 2021 Posts: 163	Hello, @furrtek has now decapped the 315-5216 chip and found a small difference with my repro based on signal analysis: the KILLGA signal also disables writes to ports $3E and $3F. https://github.com/furrtek/SiliconRE/tree/master/Sega/315-5216 This is now fixed in the equations and jed files above, many thanks to him for the feedback.

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View topic - 315-5216 and 315-5237 I/O chips reproductions (also looking for a 315-5297 chip)