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Tis the season of analysing decapped Sega chips (really, tis).

I’ve been travelling for work a few times over the last couple of months and what better way to spend late nights in a hotel room than obsessing over the I/O chip of our favourite console (no, really).

Credit to furrtek who decapped the 315-5216 I/O chip. It’s furrtek’s die shots that I have been studying to get this info.

I’ve personally wanted to see inside the I/O chip to unlock any secrets that haven’t been determined by externally probing the chip, and also to create a gate-accurate replacement of the I/O chip (note that replacement clone chips exist already on these forums).

So, lets deep dive into the Sega 315-5216 I/O chip. At least the main points anyway, to stop this post getting too long.

Overview

The 315-5216 is the early chipset of the export Master System. It was used in both PAL and NTSC Master Systems, with PAL Master Systems having additional discrete logic chips to divide the 53MHz clock into the 10.7MHz, 4.43MHz, and 3.55MHz clock signals for the VDP, PAL Subcarrier, and CPU. For PAL Master Systems, it was replaced with the later 315-5237 IO chip which moved the clock circuitry onto the chip. The 315-5216 I/O chip however continued to be used in NTSC Master Systems. The chip goes by several names including I/O chip, I/O Controller, IC4, and Gate Array.

Makers mark

The die is marked ‘A75120U © Fujitsu 1985 2C11’.

Cells and Capacity

The Gate Array core has 357 cells and is filled to only 60% of its capacity.

Port 3E bits 0 and 1

The unused bits of Port 3E, bit 0 and bit 1, are completely unused and don't even exist in silicon.

Incidentally, there are 2 areas of free cells big enough to accommodate 2 more register bits. It could be that Fujitsu kept the space free just in case Sega came back and had a use for the 2 remaining register bits of 3E.

Power On Reset values

The BIOS, RAM, and IO are enabled by default at power on and reset. The Expansion, Cartridge, and Card slots are disabled. Port 3F is initialised to 0xFF.

/KILLGA

/KILLGA inhibits /IORQ which means all IO port reads and writes from the CPU are inhibited when this pin is asserted high. This is known from external probing and used by the LionHeart Region mod chip for example to safely switch regions.

Ports DC and DD

DC and DD are implemented as 2-to-1 MUX much like the discrete 74LS157 logic of the SG-1000.

/CE0 to /CE4

/CE0 to /CE4 are implemented as OR gates between the /MREQ and /CSRAM signals and the 3E register bits. I confirmed this by probing the chip a long time ago but it’s nice to have confirmation.

Enjoy!

Super useful, thanks asynchronous (and furtek)!

asynchronous wrote

Port 3E bits 0 and 1

The unused bits of Port 3E, bit 0 and bit 1, are completely unused and don't even exist in silicon.

Very interesting.

asynchronous wrote

/KILLGA

/KILLGA inhibits /IORQ which means all IO port reads and writes from the CPU are inhibited when this pin is asserted high. This is known from external probing and used by the LionHeart Region mod chip for example to safely switch regions.

Oh right, so KILLGA actually inhibits writes to $3e and $3f too? I had assumed it only affected the $dd/$dc range but does make sense that it would gate /IORQ.

Oh also, does KILLGA also inhibit KBSEL?

asynchronous wrote

/CE0 to /CE4

/CE0 to /CE4 are implemented as OR gates between the /MREQ and /CSRAM signals and the 3E register bits. I confirmed this by probing the chip a long time ago but it’s nice to have confirmation.

Ah interesting, so I think I'd got that slightly wrong too. Looking at the schematic for SMS 1 again, I guess /CE1 must look at /CSRAM because only /CE1, /RD and /WR go into IC3, but can you confirm the exact equation for /CE0 - does it use /CSRAM or does it simply gate bit 3 of port $3e? IC2 takes /EXM2 on its /OE pin so seems like the 315-5216 might not need to decode any of the address spaces for /CE0.

willbritton wrote

Oh also, does KILLGA also inhibit KBSEL?

asynchronous wrote

/CE0 to /CE4

/CE0 to /CE4 are implemented as OR gates between the /MREQ and /CSRAM signals and the 3E register bits. I confirmed this by probing the chip a long time ago but it’s nice to have confirmation.

Ah interesting, so I think I'd got that slightly wrong too. Looking at the schematic for SMS 1 again, I guess /CE1 must look at /CSRAM because only /CE1, /RD and /WR go into IC3, but can you confirm the exact equation for /CE0 - does it use /CSRAM or does it simply gate bit 3 of port $3e? IC2 takes /EXM2 on its /OE pin so seems like the 315-5216 might not need to decode any of the address spaces for /CE0.

/KBSELL is generated by IC5. So /KILLGA has no impact on /KBSELL.

/CE0 = /MREQ OR 3E_bit2
/CE1 = /CSRAM OR 3E_bit3

I posted about the /CE lines being just an OR gate between 3E and /MREQ eons ago. It's lore to some members but the post is long forgotten. It comes up almost every time there's a 'Hey, why isn't my cartridge/mapper design working' post. But you're quite right; the combination of the /CE and /OE signals must be such that the memory doesn't output to the data bus in the SYS RAM address space 0xC000 - 0xFFFF.

asynchronous wrote

/KBSELL is generated by IC5. So /KILLGA has no impact on /KBSELL.

Oh yeah, right you are! It feels counterintuitive that it's coming from IC5 but perhaps they ran out of pins on IC4!

asynchronous wrote

I posted about the /CE lines being just an OR gate between 3E and /MREQ eons ago. It's lore to some members but the post is long forgotten. It comes up almost every time there's a 'Hey, why isn't my cartridge/mapper design working' post.

For sure it does seem to catch people out with respect to /CE3 in particular, although with a little thought it could only work the way it does.

The mistake I made was thinking that all the /CEx lines worked in the same way but /CE1 is slightly different as you have explained.

I've made a revision to the Development/BusSignals which I think covers the corrections - would be grateful for a second pair of eyes to make sure I've got it all right.

EDIT: P.S. minor correction to your original post, I think you mean 74LS257 rather than 157.

Didn't want to make a new topic so I was looking for the best one to reply to about the 315-5216 schematics I just finished.

And what do I find ? Asynchronous already giving all the details :)

Here it is anyways, in case anyone wants to see how things are done at the gate level:
https://github.com/furrtek/SiliconRE/tree/master/Sega/315-5216

I don't really see the point of having the Z80 data bus output lines being fed back into the input lines for the bidirectionnal pins. Other Fujitsu chips I've seen don't have that, so Sega deliberately designed it that way.

Also did that /HL pin ever get any use ?

furrtek wrote

Also did that /HL pin ever get any use ?

Yep, every time the CRT beam crossed the light phaser beam.

Author	Message
asynchronous Joined: 14 Aug 2000 Posts: 752 Location: Adelaide, Australia	315-5216 Deep Dive Posted: Fri Jun 21, 2024 3:52 pm
	Tis the season of analysing decapped Sega chips (really, tis). I’ve been travelling for work a few times over the last couple of months and what better way to spend late nights in a hotel room than obsessing over the I/O chip of our favourite console (no, really). Credit to furrtek who decapped the 315-5216 I/O chip. It’s furrtek’s die shots that I have been studying to get this info. I’ve personally wanted to see inside the I/O chip to unlock any secrets that haven’t been determined by externally probing the chip, and also to create a gate-accurate replacement of the I/O chip (note that replacement clone chips exist already on these forums). So, lets deep dive into the Sega 315-5216 I/O chip. At least the main points anyway, to stop this post getting too long. Overview The 315-5216 is the early chipset of the export Master System. It was used in both PAL and NTSC Master Systems, with PAL Master Systems having additional discrete logic chips to divide the 53MHz clock into the 10.7MHz, 4.43MHz, and 3.55MHz clock signals for the VDP, PAL Subcarrier, and CPU. For PAL Master Systems, it was replaced with the later 315-5237 IO chip which moved the clock circuitry onto the chip. The 315-5216 I/O chip however continued to be used in NTSC Master Systems. The chip goes by several names including I/O chip, I/O Controller, IC4, and Gate Array. Makers mark The die is marked ‘A75120U © Fujitsu 1985 2C11’. Cells and Capacity The Gate Array core has 357 cells and is filled to only 60% of its capacity. Port 3E bits 0 and 1 The unused bits of Port 3E, bit 0 and bit 1, are completely unused and don't even exist in silicon. Incidentally, there are 2 areas of free cells big enough to accommodate 2 more register bits. It could be that Fujitsu kept the space free just in case Sega came back and had a use for the 2 remaining register bits of 3E. Power On Reset values The BIOS, RAM, and IO are enabled by default at power on and reset. The Expansion, Cartridge, and Card slots are disabled. Port 3F is initialised to 0xFF. /KILLGA /KILLGA inhibits /IORQ which means all IO port reads and writes from the CPU are inhibited when this pin is asserted high. This is known from external probing and used by the LionHeart Region mod chip for example to safely switch regions. Ports DC and DD DC and DD are implemented as 2-to-1 MUX much like the discrete 74LS157 logic of the SG-1000. /CE0 to /CE4 /CE0 to /CE4 are implemented as OR gates between the /MREQ and /CSRAM signals and the 3E register bits. I confirmed this by probing the chip a long time ago but it’s nice to have confirmation. Enjoy!

willbritton Joined: 06 Mar 2022 Posts: 697 Location: London, UK	Posted: Fri Jun 21, 2024 4:33 pm
	Super useful, thanks asynchronous (and furtek)! asynchronous wrote Port 3E bits 0 and 1 The unused bits of Port 3E, bit 0 and bit 1, are completely unused and don't even exist in silicon. Very interesting. asynchronous wrote /KILLGA /KILLGA inhibits /IORQ which means all IO port reads and writes from the CPU are inhibited when this pin is asserted high. This is known from external probing and used by the LionHeart Region mod chip for example to safely switch regions. Oh right, so KILLGA actually inhibits writes to $3e and $3f too? I had assumed it only affected the $dd/$dc range but does make sense that it would gate /IORQ. Oh also, does KILLGA also inhibit KBSEL? asynchronous wrote /CE0 to /CE4 /CE0 to /CE4 are implemented as OR gates between the /MREQ and /CSRAM signals and the 3E register bits. I confirmed this by probing the chip a long time ago but it’s nice to have confirmation. Ah interesting, so I think I'd got that slightly wrong too. Looking at the schematic for SMS 1 again, I guess /CE1 must look at /CSRAM because only /CE1, /RD and /WR go into IC3, but can you confirm the exact equation for /CE0 - does it use /CSRAM or does it simply gate bit 3 of port $3e? IC2 takes /EXM2 on its /OE pin so seems like the 315-5216 might not need to decode any of the address spaces for /CE0.

asynchronous Joined: 14 Aug 2000 Posts: 752 Location: Adelaide, Australia	315-5216 Deep Dive Posted: Sat Jun 22, 2024 1:54 am
	willbritton wrote Oh also, does KILLGA also inhibit KBSEL? asynchronous wrote /CE0 to /CE4 /CE0 to /CE4 are implemented as OR gates between the /MREQ and /CSRAM signals and the 3E register bits. I confirmed this by probing the chip a long time ago but it’s nice to have confirmation. Ah interesting, so I think I'd got that slightly wrong too. Looking at the schematic for SMS 1 again, I guess /CE1 must look at /CSRAM because only /CE1, /RD and /WR go into IC3, but can you confirm the exact equation for /CE0 - does it use /CSRAM or does it simply gate bit 3 of port $3e? IC2 takes /EXM2 on its /OE pin so seems like the 315-5216 might not need to decode any of the address spaces for /CE0. /KBSELL is generated by IC5. So /KILLGA has no impact on /KBSELL. /CE0 = /MREQ OR 3E_bit2 /CE1 = /CSRAM OR 3E_bit3 I posted about the /CE lines being just an OR gate between 3E and /MREQ eons ago. It's lore to some members but the post is long forgotten. It comes up almost every time there's a 'Hey, why isn't my cartridge/mapper design working' post. But you're quite right; the combination of the /CE and /OE signals must be such that the memory doesn't output to the data bus in the SYS RAM address space 0xC000 - 0xFFFF.

willbritton Joined: 06 Mar 2022 Posts: 697 Location: London, UK	Posted: Sat Jun 22, 2024 11:56 am
	asynchronous wrote /KBSELL is generated by IC5. So /KILLGA has no impact on /KBSELL. Oh yeah, right you are! It feels counterintuitive that it's coming from IC5 but perhaps they ran out of pins on IC4! asynchronous wrote I posted about the /CE lines being just an OR gate between 3E and /MREQ eons ago. It's lore to some members but the post is long forgotten. It comes up almost every time there's a 'Hey, why isn't my cartridge/mapper design working' post. For sure it does seem to catch people out with respect to /CE3 in particular, although with a little thought it could only work the way it does. The mistake I made was thinking that all the /CEx lines worked in the same way but /CE1 is slightly different as you have explained. I've made a revision to the Development/BusSignals which I think covers the corrections - would be grateful for a second pair of eyes to make sure I've got it all right. EDIT: P.S. minor correction to your original post, I think you mean 74LS257 rather than 157.

furrtek Joined: 05 Mar 2006 Posts: 54 Location: France	Posted: Fri Aug 02, 2024 3:20 am
furrtek Joined: 05 Mar 2006 Posts: 54 Location: France	Didn't want to make a new topic so I was looking for the best one to reply to about the 315-5216 schematics I just finished. And what do I find ? Asynchronous already giving all the details :) Here it is anyways, in case anyone wants to see how things are done at the gate level: https://github.com/furrtek/SiliconRE/tree/master/Sega/315-5216 I don't really see the point of having the Z80 data bus output lines being fed back into the input lines for the bidirectionnal pins. Other Fujitsu chips I've seen don't have that, so Sega deliberately designed it that way. Also did that /HL pin ever get any use ?

asynchronous Joined: 14 Aug 2000 Posts: 752 Location: Adelaide, Australia	315-5216 Deep Dive Posted: Fri Aug 02, 2024 5:51 am
	furrtek wrote Also did that /HL pin ever get any use ? Yep, every time the CRT beam crossed the light phaser beam.

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